The rapid advancement of wearable electronics in smart textiles has driven the need for highly efficient and precise timing solutions. Traditional crystal oscillators, while accurate, are too bulky for seamless integration into fabric-based computing environments. My research addresses this challenge by designing a tunable, ultra-low power on-chip oscillator, specifically optimized for real-time synchronization in multi-chip fabric-integrated systems.
This work introduces a current-starved ring oscillator (CSRO) running in sub-threshold weak inversion, achieving an exceptionally low power consumption of 170 femtojoules per cycle. Operating at 1.1V, the oscillator provides a frequency range of 88.35 kHz to 108.7 kHz with an ultra-fine tuning step size of 80 Hz (0.08%), ensuring precise clock adaptability for dynamic sensing and processing tasks.
Designed for integration within ARM Cortex M0+ based System-on-Chip (SoC) architectures, the oscillator enables efficient multi-chip synchronization, ensuring timing accuracy within ±100 microseconds across a network of embedded sensors. This solution is a significant step forward for next-generation textile computing, offering a compact, energy-efficient, and scalable clocking solution for real-time applications.
Thesis Defence Slide: Ms_presentation_Final.pptx
More information will be updated soon as paper is available online.
The Current Mode Bandgap Reference (BGR) Circuit in the provided schematic is designed to generate a stable reference voltage with minimal temperature variation and high power supply rejection. The design employs a current-mode architecture, which enhances precision and robustness against variations in process, voltage, and temperature (PVT). The circuit consists of a startup network, a current mirror biasing stage, a bandgap core, and an output buffer. The startup circuit ensures proper initialization by preventing the circuit from settling at an undesired zero-current state. The current mirror structure enforces proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) currents, which combine to produce a temperature-independent voltage reference.
From the DC response graph, the reference voltage exhibits a parabolic temperature coefficient, peaking at around 30°C before slightly decreasing, confirming an optimized temperature compensation technique. The stability analysis, as shown in the phase margin plot, indicates a phase margin of approximately 74.83 degrees at 23.907 MHz, ensuring a stable closed-loop operation. The gain margin of 25.1041 dB at 291.567 MHz further verifies robustness against instability. The loop gain response suggests strong DC gain for high accuracy, with a controlled roll-off at higher frequencies, avoiding excessive peaking that could lead to oscillations.
Overview:
A Flash Analog-to-Digital Converter (ADC) is the fastest ADC architecture, utilizing a parallel conversion technique to achieve extremely high-speed data acquisition.
Working Principle:
Uses 2ⁿ - 1 comparators for an n-bit ADC. A resistor ladder generates reference voltages. Each comparator compares the input voltage (V_in) with its reference voltage. The outputs of the comparators form a thermometer code, which is then converted into a binary output using an encoder.
Key Components: Resistor Ladder, Comparators (2 stage opamp has been used here as comparator), Thermometer-to-Binary Encoder