Independent Study
Submissions
Instructor: Dr Benton Calhoun
Table of Content
Wearable e-textile systems often feature multi-chip configurations, where sensors, actuators, and processing units are distributed across the fabric. Timing synchronization between these chips is essential for reliable operation. Current approaches rely on commercial crystal oscillators, where each chip uses an individual oscillator for timing. This method not only increases the overall system size but also introduces inefficiencies in power and scalability.
A promising alternative is to adopt a hybrid timing approach: one chip within the system employs a traditional crystal oscillator, while the others use tunable on-chip oscillators synchronized with the primary clock source. Such a design reduces the physical footprint, power consumption, and cost while maintaining precise timing. However, implementing a reliable, low-power, and fine-tunable on-chip oscillator remains a significant challenge, particularly in dynamic and resource-constrained environments.
This research is motivated by the need to design an oscillator operating at subthreshold voltages, ensuring ultra-low power consumption and fine-tuning capabilities. The ultimate goal is to integrate this oscillator into a fabric-based multi-chip network, enabling real-time synchronization with minimal overhead.
Wearable electronics are revolutionizing technology by enabling innovative applications such as health monitoring, smart textiles, and human-machine interaction. These systems demand compact, energy-efficient, and precise timing solutions for seamless operation and data synchronization. Traditional crystal oscillators, while accurate, are unsuitable for fabric integration due to their bulkiness, high power consumption, and limited scalability.
This independent study focused on designing and validating a tunable Current Starved Ring Oscillator (CSRO) that meets the specific needs of e-textile systems. The CSRO was designed to provide ultra-low power consumption, precise tuning, and compact integration for multi-chip networks embedded within fabrics.