This project presents a new hybrid MDLL (Multiplying Delay lock loop) architecture that can reduce the jitter of an on-chip oscillator circuit with low power consumption which comprises a dual feedback loop feature. The primary negative feedback loops reduce the jitter within the MDLL whereas the additional negative feedback loops minimize the variance in delay time across each stage of delay. Incorporating both sets of negative feedback loops in a DLL further diminishes the clock signal jitter. Measurement results of the hybrid MDLL-based clock generator with dual negative feedback loops designed in 65nm TSMC process show 2.5-ps periodic jitter and 9.32-fs rms jitter at 200MHz with a power consumption of 328 µW. 

Feedbacks:

• publications: Good.

• review quality: Your summaries are pretty good and focus on metrics

• simulation quantity: built working basic RO. One comparison table.

• Simulation quality: Good progress was made to get a working component, although it's simple. Would be nice to see you exercise some design tradeoffs. The P-f plot is unclear; is it non-monotonic? Seems like something could be wrong.

• The comparison table would be better to show as some plots that compare metrics to show a design space; where in the design space are you trying to explore for your project?

• report: Good simple summary of prior work. Work on getting more specific about the research questions or interesting tradeoffs you will explore

• tasks: Too simple

• You need to be more specific with a target research question or tradeoff(s) that you plan to explore before the proposal.

Feedbacks:

• Problem - your research question deals with lower jitter and power

• Approach - The approach explores hybrid architectures

• Design - clock gen circuits

• Novelty - Pulls from several references

• Outcomes -

• Refs - a SOA scatter plot

• wiki page - not created

• Plan - Simple - I suggest adding detail.

• Timeline/tasks -

• Simulations - Const-gm and RO; Need to make rapid progress with sims! Need to figure out how to simulate jitter.

Feedbacks:

more pubs: ok

Design description:

Simulation quantity:

-- Good; multiple components working along with DLL

Simulation quality:

-- schematics hard to read; plots hard to see legends; you MUST clean up the quality, especially of the schematics -- Fig 4, 8: what does negative efficiency mean?! -- Fig 7: why is the ripple negative?

-- it is not clear that you are using "efficiency" and "ripple" correctly; the plots are wrong if you are using those terms in the conventional definitions.

Report:

-- Very nice progress!

-- Make sure you do a good job telling the story of your project; WHY are you investigating this? What is the hypothesis / claim? What reasons do you have for exploring this? How well (or not) is it working? How does it compare to prior work (very important!)?